When:
May 8, 2017 @ 2:30 PM – 4:00 PM
Where:
Room: EB1-116, Bldg: Engineering Building 1
Co-sponsored by: American University of Sharjah Extension of Moore’s curve down to sub-nanoscale dimensions would lead to the anticipated delivery of over 100 Billion transistors with hundreds of optimized cores on a single chip. However, CMOS technologies are moving towards the fundamental limits of performance, energy efficiency, and physical and material reliability. In Von Neumann architecture, the physical and function separation of the central processing and memory units limits execution speed and imposes heavy energy overheads. CMOS technology is, therefore, confined in the medium-performance and medium-power range due to the conflicting impacts of supply and frequency scaling on performance and energy efficiency. There has been a great demand to study the two extreme ends of the design spectrum, namely, the ultra-low-power (ULP) with acceptable performance at one end and extremely high-performance with manageable power at the other. In future, a third direction is going to emerge to push for high-performance applications with low consumption. Many ultra-low-power (ULP) circuits would be operated in the subthreshold region of the conventional transistors leading to extremely low energy consumption that can be scavenged from the natural renewable sources. The biggest challenge for subthreshold design is to overcome the thermionic limit (60mV/decade) of the conventional bulk and emerging MOSFET technologies. This project seeks alternative technology for the next generation low-power and ULP logic, memory and sensing applications. The technical objectives of this project are to introduce a new field effect transistor (FET) technology to utilize the negative capacitance (NC) of ferroelectric materials and to demonstrate innovative circuits, systems and CAD development approaches using the new device. The proposed device is named Silicon on Ferroelectric Insulator Filed Effect Transistor (SOFFET). The proposed SOFFET, which combines the emerging concept of negative capacitance based transistor with the conventional SOI technology, replaces buried SiO2 layer of SOI device by a ferroelectric insulator. Due to the inherent hysteresis property of the ferroelectric material, it would introduce an NC effect to provide internal signal boosting leading to steeper subthreshold slope (lower subthreshold swing) and higher device gain (ION/IOFF ratio). CMOS technology is approaching its fundamental physical and efficiency limits due to the thermionic emission limit of the subthreshold swing (S = 60mV/decade – known as the Boltzmann tyranny) imposed by thermal potential (kT/q). Even with the excellent electrostatic and transport properties of the most recent tri-gate FinFET structure, no MOSFET device can overcome this theoretical limit. Recently, there has been a surge of interest to utilize the NC effect of ferroelectric material in the gate-stack of a transistor to cross this barrier. The concept that has become known as NCFET or FeFET faces severe stability and reliability issues. Here, the transformative concept is the utilization of ferroelectric NC effect in the body stack of a SOI device to keep the new device compatible to the commodity CMOS process while avoiding the reliability and stability concerns of the gate-stack NCFET. The proposed SOFFET has the potential to take the value of S below 20 mV/decade (very steep slope and high gain). It would also offer faster speed, lower threshold and supply voltages, higher integration density, lower leakage, and higher ON current. Perhaps the most notable feature of SOFFET is its compatibility to CMOS process, which makes it very attractive to the industry for near future commercialization. In addition to the validation of the new concept, the PI will focus on developing closed-form models to analyze the current-voltage (I-V) characteristics and other static and dynamic behaviors of the device both in the subthreshold and saturation regions. These models would be used to analyze the dependence of device behaviors on material, geometric and environmental parameters including thermal stress and radiation. The project will also focus on developing methodologies to optimize the thickness of the ferroelectric film, dielectric property of the insulator, and the doping profile of the device. The PI will demonstrate representative logic circuits using the SOFFET. Applications of the SOFFET in a new class of power gating and dynamic thermal management techniques will also be investigated. To accomplish this goal a double-gate SOFFET design will be introduced to take the advantage of multi-threshold CMOS (MTCMOS) technique without the overheads of the conventional sleep transistors and power gating circuits. The new approach will combine the functionalities of the sleep transistors with the logic devices. This project is currently funded by National Science Foundation (NSF 2016 Grant # 1617443), Washington DC, USA. Speaker(s): Dr Masud H Chowdhury, Location: Room: EB1-116 Bldg: Engineering Building 1 American University of Sharjah Engineering College Sharjah, Kansas 26666 Sharjah
